The present application relates to power devices which include trenches having empty space zones therein, to methods for making such devices, and to other related methods.
Note that the points discussed below may reflect the hindsight gained from the disclosed inventions, and are not necessarily admitted to be prior art.
Power MOSFETs are widely used as switching devices in many electronic applications. In order to minimize the conduction power loss it is desirable that power MOSFETs have a low specific on-resistance (RSP or R*A), which is defined as the product of the on-resistance of the MOSFET multiplied by the active die area. In general, the on-resistance of a power MOSFET is dominated by the channel and drift region resistances.
The most common way to reduce the RSP is to shrink the device's unit cell pitch and increase the packing density or number of cells per unit area. However, as the cell density increases, the associated intrinsic capacitances of device, such as the gate-to-source capacitance (Cgs), the gate-to-drain capacitance (Cgd), the total input capacitance (Ciss) and the total output capacitance (Coss), also increase. In consequence, the switching power loss of device will increase which is undesirable. In many switching regulation applications such as synchronous buck dc-dc converters used in mobile products, MOSFETs are required to operate at high switching frequencies approaching the range of 1 MHz. Therefore, it is desirable to minimize the total switching or dynamic power loss governed by these capacitances.
Currently, there are two common techniques to improve the switching performance of power MOSFETs. The first one is the trench-gated MOSFET with thick bottom oxide (BOX), as shown in FIG. 1(a) (taken from U.S. patent application Ser. No. 12/431,852). In the structure of this Figure, a gate electrode 140 (typically polysilicon) is positioned inside a trench, and capacitively coupled to the adjacent p-type body region 120. When the gate 140 is at a sufficiently positive voltage, the nearest part of the body region 120 will be inverted to form a channel, so that conduction is possible. Specifically, electrons will pass from n+ source 130, through the vertical channel, into the drift region 112, and down to the n+ drain diffusion 110. A backside connection 102 makes contact to the drain diffusion 110, and a frontside connection 104 makes contact to the source diffusion 130. The frontside connection 104 also makes contact to a p+ body contact diffusion 122, and therethrough to body diffusion 120. The thick bottom oxide 184 helps to decouple the gate from the drain.
The second common approach is the split poly gated MOSFET structure, in which a bottom poly region 150, connected to the source electrode, lies below the gate. An example of this, along the lines of U.S. Pat. No. 5,998,833 and/or U.S. Pat. No. 6,683,346, is shown in FIG. 1(b). This bottom region 150 may be referred to as a shield plate, since it improves shielding between the drain and the gate, and hence reduces the Miller charge.
In the first technique, the gate-to-drain capacitance, Cgd, is dependent on the trench width, BOX thickness and the dielectric constant of BOX layer. Narrower trench and thicker BOX are required in order to achieve a very low Qgd number. Unfortunately, a narrow trench will put a limitation on the maximum BOX thickness used in this structure without incompletely filling of the trench bottom.
The resistance of the drift region is also a significant concern in power MOSFETs. One approach to reducing the drift region resistance uses the so called superjunction structure. A superjunction device is constructed by paralleling relatively highly doped p-type and n-type layers or pillars in an alternating pattern. The doping concentrations of the n-type pillar (the n-type drift region), for the same breakdown voltage, can be significantly higher than that of a conventional drift region, as long as the total charge of the n-type pillar is balanced with the charge in the p-type pillar. In order to fully realize the merit of the superjunction, it is desirable to pack many pillars in a given area to achieve a lower specific on-resistance RSP. However, the minimum achievable widths, in device manufacturing, of the n-type and p-type pillars set a limitation on the reducing the cell pitch and scaling the device.
A recently published application (US application 20080164518), as shown in FIG. 1(c), has addressed this issue by incorporating permanent positive charges (QF) in trenches filled with dielectric material such as silicon oxide. The permanent charge also forms an electrically induced drift region by creating an inversion layer between the oxide and the P layer. By making use of this new concept, the scaling limitation due to inter-diffusion of p-type pillar and n-type pillar can be significantly reduced. Consequently, a small cell pitch and high packing density of pillars, as well as a large channel cross-section (for a given total surface area) can be realized. This reduces the device's total on resistance and its RSP.
In the MOSFET structure shown in FIG. 1(c), the breakdown voltage is proportional to the trench depth and its RSP is proportional to the cell pitch. As the trench depth increases and cell pitch reduces, the trench becomes deep and narrow. As the trench depth to width aspect ratio increases it becomes more difficult to completely fill it with dielectric material, and manufacturing the device becomes a problem. Furthermore, a void may exist in the trench that precludes forming a gate electrode within the trench, since it cannot be reliably reproduced.
Some of the present inventors have previously proposed power devices which include dielectric-lined trenches with empty space zones, as in PCT application WO2008086348. In this application, note that FIG. 2B shows a void in the charge control trenches, and the accompanying description mentions the possibility of multiple voids. FIGS. 43B, 43C, and 43D of this earlier application all show voids in a trench below a predominantly planar gate (but note that gate sags into trench a little). FIGS. 2B, 38N, 44L, and 45L of this earlier application each show devices with a void in the Recessed Field Plate trenches, but not in the gate trenches. This earlier application, and all of its priority applications, are hereby incorporated by reference. That application is commonly owned with the present application, and Applicants reserve the right to claim priority from that application in all countries where such priority is available.